1. We had some discussion on the digital layout. Some DRC violations were reported, related to the NWELL clearance. It seems we had to waive those violations in this version.

  2. Post simulation of 64 pixels were reported, and two versions of address buffers were reported. The tristate buffer has better performance, without any modification of the interface.

  3. Some test features were added according to the reviewer's advice. The periphery layout is almost ready for final integration.

  4. We are still trying to integrate every block to get the final layout of the chip ready before May 20. All designs, including schematic/netlist and layout will be collected before the end of this week, and then integrated to get the final chip.