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MOST2 chip design meeting

Name: MOST2 chip design meeting
Start: 2019-05-23T08:00:00+08:00
End: 2019-05-23T18:00:00+08:00
Location: No location set

Thursday 23 May 2019, 08:00 → 18:00 Asia/Shanghai

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1. Wei Wei reported current status of the chip layout. Some necessary layout modification was found during the block integration. The pixel array & periphery layout was LVS clean (nearly). The interconnections between the pixel array & periphery seems ok and part of the LVS was also passed.

The fully integrated chip layout is estimated to be ready by the end of this week.

The cross verification is ongoing in parallel.

2. We had a discussion with Raimon about the tapeout status. The estimated submission date is about June 10

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