1. Tianya reported that the suspicious bug about the FE-I3 address decoder turned out to be without (obvious) problem. Further verification will be done.
2. Zhang Ying reported some layout modification status on pixel array. Most of the DRC violations were fixed, however some LVS errors left. It maybe because of the wrong reference of the libs.
3. The PLL and serializer of the data interface layout has been done, only the CML driver left. We had a discussion on the load model about the L & C, when consider the PCB and module data transmission.
4. We had a discussion on how to proceed the payment and paper work for this tapeout. We need to confirm some of the details from both side.