MOST2 chip design meeting

Name: MOST2 chip design meeting
Start: 2019-06-06T08:00:00+08:00
End: 2019-06-06T18:00:00+08:00
Location: No location set

Thursday 6 Jun 2019, 08:00 → 18:00 Asia/Shanghai

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1. Wei wei reported the status of the tapeout. The gds is ready, and only the drc violations due to the CIS process were left, others were clean.
Some softchk results were still reported in the LVS check. Part of them were from the AND gate and the other s were from the IO PAD. Both of them can be ignored.
2. Raimon reported the current status with TJ. Since no more problems were reported from the design team, we are going to finally submit the GDS, today.
IFAE will sign a first contract with TJ soon, and see how to proceed for the further steps.
3. We initiated a nomination for the chip series for MOST2, and may vote in the following weeks.

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