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1. The chip name was final decided to be TaichuPix1.
2. Tianya reported some simulation evaluation of the power dissipation. For the Alpide-like scheme, the current seems high during the setup phase, although it will goes back to the normal level after the power-up configuration. Xiaomin suggested to simulate the latch inside the pixel, because it has the potential issues of large leakage current.
3. Xiaomin proposed some improvement directions for the periphery logic in the next version. Area is an issue, if we are aiming for a total insensitive width within 1mm. Power is another issue. In the current version, the clock tree is the most power consuming block. We can image some more careful design of the clock gating and distribution. We can also think some more trigger-focused scheme to save power, while the triggerless scheme is too power consuming.
If we can accept a larger deadtime, to share some logic between two double-column is also an idea to save area and power. However, this should be discussed from the physics simulation.
4. Zhang Ying is preparing the user manual for the test, while most of the user manual from every block have been collected. A preliminary design of the test board PCB is also provided by Jianing for further discussions.