eFEX preproduction module design and test

by Dr Weiming Qian (Rutherford Appleton Laboratory)

Wednesday 28 Aug 2019, 10:00 → 12:00 Asia/Shanghai

B326 (IHEP main building)

ABSTRACT: Electron Feature Extractor (eFEX) is one of the core subsystems for the Phase-I upgrade of the ATLAS Level-1 Calorimeter Trigger. In Run 3, eFEX will identify isolated e/g and t particles with much higher discriminatory power using finer granularity information from calorimeters. eFEX subsystem consists of 24 eFEX modules housed in 2 ATCA shelves. Each eFEX module has up to 200 optical input/output links and more than 400 on-board electrical fan-out links all running at 11.2Gbps. Four eFEX pre-production modules have been made and tested. Presented here are hardware and firmware design experience and test results of the eFEX pre-production modules. SUMMARY: The ATLAS Level-I Calorimeter Trigger Phase-I upgrade consists of three Feature Extractor (FEX) subsystems: eFEX, jFEX and gFEX. The function of eFEX is to identify the isolated energy deposits indicative of electrons, photons and tau particles in the electromagnetic and hadronic calorimeters. To cope with the increased pileup in Run 3, eFEX runs more complicated algorithms with higher discriminatory power on the finer granularity calorimeter data to retain the trigger sensitivity to the electroweak physics processes at low energy threshold. In Run 3, the ATLAS front-end detector electronics will remain largly unchanged and the ATLAS Level-1 latency will still be limited to 2.5 us. The latency budget for the eFEX subsystem is only 13.5 Bunch Crossings (BC). To meet this tight latency requirement, all the eFEX algorithms are implemented in firmware running in modern FPGAs. The whole eFEX subsystem is devided into 24 eFEX modules housed in two ATCA shelves, and each eFEX module holds 4 algorithm processing FPGAs (XCV550T) and one control FPGA. Each module receives data on up to 136 fibre links (11.2 Gb/s) covering an calorimeter area of up to 1.7 x 1.0 (eta x phi). As eFEX algorithms are based on overlapping windows, the majority of input high-speed links are fanned out electrically on-board to multiple FPGAs for the algorithm window environment data sharing, resulting in more than 400 differential high-speed link routing on a single eFEX module. The Tigger OBjects (TOBs) caculated by eFEX algrithms are first merged and sorted across the whole module and only the most energetic TOBs are sent to L1Topo subsystem over up to 48 fibre links (11.2Gb/s). Upon each L1A, data are collected from various processing stages on the eFEX realtime path, formatted and sent to L1Calo RODs. This readout function is important for trigger validation and trigger performance analysis. Each eFEX module sends its readout data over 8 electrical links (6.4Gb/s) on the ATCA backplane using multi-lane AURORA protocol, which provides enough bandwidth for both Phase-I and Phase-II readout requirements. The eFEX module control and configuration is done via the IPBus firmware implemented in the control FPGA, which isolates OS software maintenance issues from the eFEX hardware system. Misson critical parameters of an eFEX module are monitored by ATLAS DCS system via a on-board IPMC, which would shut down the module power to prevent hardware damage in case of critical errors such as overvoltage or overtemperature. Non-mission critical parameters on a eFEX module are collected via IPBus and sent to DCS system. Following the successful Final Design Review of eFEX project in Dec 2018, four pre-production eFEX module have been designed and , comprehensive firmware has been developed, and systematic integration tests have been done. This presentation will report the experience of eFEX hardware and firmware development and the integration test results.

Slides WeimingQianCV_IHEP.pdf