MOST2 chip design meeting

Monday 9 Sep 2019, 08:00 → 18:00 Asia/Shanghai

  Wei Wei reported some simulation results concerning the high-z state. Both FE-I3 and ALPIDE will face the high-z problem, when there is no hit for a time longer than ~400us, and the power dissipation will go up(current).

  The pull-up architecture was tried to avoid the high-z state, and found effective. However, the new problem is that, the address encoder will lose the capability of "latching", thus the timing should be modified. Preliminary attempt was also proved, that the "read" signal was modified according to the new proposed scheme.

  Xiaomin suggested that we can also try with controlled pull-up architecture. For example only to pull-up when FASTOR is invalid. The uncontrolled pull-up should also be verified with real parasitic parameter, to see if its response is too slow to cause any problem. 

08:00 → 08:20 timing

Slides Weiw_20190909.ppt