1. IE browser is NOT supported anymore. Please use Chrome, Firefox or Edge instead.
2. If you are a new user, please register to get an IHEP SSO account through https://login.ihep.ac.cn/registlight.jsp Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
4. The max file size allowed for upload is 100 Mb.

MOST2 chip design meeting

Asia/Shanghai

 1. The connections, routing, and the material budget were roughly discussed. However, the discussion was only an initiation, and we agreed to discuss more details next week, with more interface input. All interface input should be written down in document.

  2. Li Long reported some TCAD simulation, especially the TID behavior on sensors. A general conclusion was the charge collection will have little impact while the leakage current and capacitance will increase a lot. However, some details for the simulation settings were discussed, including the TID models, the pixel pitch, the field oxide, the leakage current, and the breakdown voltage. They seemed not well matched with what was reported, and the value of the doping profile impacts a lot. Further simulation will be made and compared with the reported.

  3. Tianya reported some test status in IFAE for the pixel digital circuit. The row and column seemed to be capable to be scanned, and the FEI3-like part showed more promising results. However some problems still needs to be further understood.

  4. Xiaomin also briefly reported the test status. The trigger mode was found functional that can mask all the output from ALPIDE-like columns, which were problematic. The next step will probably be the attempt by using analog calibration input, rather than digital, for less crosstalk.

  5. The test board for Tcpx2 was almost finished by Jianing. We had a further discussion on the layout. Jianing will try to move the DAC a little further away from the chip area. We also agreed not to make a hole on the PCB under the chip for this version.

  6. Xiaoting reported some test status for the PLL. The lock range of the PLL agreed with what was tested before. When doing the jitter measurement, it was found that the test results were not good, maybe due to the slow CMOS output. When probing the eye diagram by the differential probers, it was found the eye diagram was stable at the frequency of 2.24GHz. It will get worse at 3.36GHz, and eye closed at 4.48GHz, showing the most stable frequency will be 2.24GHz. 

There are minutes attached to this event. Show them.