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workshop link: https://indico.ihep.ac.cn/event/22089/
Hangzhou Platinum Hanjue Hotel
The Technical Design Report (TDR) for the Circular Electron Positron Collider (CEPC) accelerator, designed as a Higgs and high-luminosity Z factory, was released in 2023. The baseline detector concept includes a large 3D tracking system, featuring a high-precision Time Projection Chamber (TPC) as one of the main tracking detectors, embedded in a 3.0T solenoid field. This design is also well-suited for the accelerator's operation at Tera-Z. The TPC requires a longitudinal time resolution of less than 100 ns, while the physics goals demand a Particle Identification (PID) resolution of less than 3%.
In this talk, we will present the feasibility and progress of high-precision TPC technology for the CEPC, including its application at Tera-Z. Key parameters such as spatial resolution, PID with good separation power, and drift velocity were studied through simulations and measurements using a TPC prototype with a 500 mm drift length. We will review the track reconstruction performance results and outline the next steps toward CEPC physics, the detector TDR, and TPC construction.
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Particle identification (PID) is crucial for the CEPC physics, with a promising breakthrough involving cluster counting. This method quantifies primary ionizations along a particle’s trajectory in the gaseous tracker (DC/TPC), moving beyond traditional dE/dx measurements. However, a significant challenge in cluster counting is the development of an efficient reconstruction algorithm to accurately recover cluster signals from the electronics readouts.
Machine learning algorithms have emerged as the state-of-the-art approach in PID. For the DC, an updated supervised model based on Long Short-Term Memory (LSTM) and Dynamic Graph Convolutional Neural Networks (DGCNN) has achieved a remarkable 10% improvement in separating K mesons from π mesons compared to traditional methods. When working with test beam data samples collected at CERN, label scarcity and data/model discrepancies pose challenges. To address this, a semi-supervised domain adaptation model has been developed, leveraging Optimal Transport to transfer information between simulation and real data domains. This model is validated using pseudo data and further applied to real data, demonstrating superior performance over traditional methods across varying track lengths.
Additionally, a study involving the TPC has been conducted, and I will also present recent progress in developing machine-learning-based reconstruction algorithms for the TPC.
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A low-power front-end ASIC, named WASA, has been developed for the CEPC Time Projection Chamber (TPC). Power consumption is a critical concern and has been addressed by utilizing a 65 nm CMOS process and a circuit structure with simple analog circuits. Three prototype ASIC chips have been designed and fabricated: a 5-channel analog front-end (AFE) chip, a SAR ADC chip, and a mixed-signal chip that integrates both the AFE and ADC. In this talk, we will report on the design and test results of the AFE and SAR ADC chips.
The power consumption of the AFE and SAR ADC cores was measured at 2.0 mW and 1.0 mW per channel, respectively. The gain and Equivalent Noise Charge (ENC) of the AFE were 8.91 mV/fC and 644 electrons at 10 pF input capacitance, which includes the contribution of 460 electrons from the external buffer used for testing purposes. The Integral Non-Linearity (INL) was less than 0.5% for a dynamic range of 145 fC. No significant performance degradation was observed after exposure to a total dose of up to 1 Mrad (Si).
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A global community of physicists specializing in Lepton Collider Time Projection Chambers (TPC) is working to realize an exceptional physics program at the energy frontier, particularly for electron-positron collisions in the International Linear Collider (ILC) and the Circular Electron Positron Collider (CEPC). A large TPC prototype, tested in a 1.0 T magnetic field, accommodates up to seven identical Micro Pattern Gaseous Detector (MPGD) readout modules. This prototype has been studied using a 5 GeV electron beam at DESY. Several successful beam test experiments have measured key performance metrics, such as drift velocity, spatial resolution, and dE/dx resolution, using different readout technologies (GEM, Resistive Micromegas, and GridPix) with a monolithic cooling plate in 2-phase CO2.
In the updated CEPC Physics and Detector Technical Design Report (TDR), the TPC is described as having a cylindrical drift volume with an inner radius of 0.6 m, an outer radius of 1.8 m, and a half-length of 2.9 m. This design significantly enlarges the tracking acceptance (cosθ ~0.98). The TPC can provide up to thousands of 3D space points, with a single hit resolution of approximately 100 µm in the r-φ plane. There are two options for the readout structure: pad and pixel, both of which are promising technologies, especially at the high-luminosity Z-pole.
In this talk, we will present track reconstruction performance results and outline the next steps for developing pad/pixelated TPC technology for future lepton colliders.
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Future circular electron-positron collider has been proposed as both Higgs factories and high-luminosity Z factories. The conceptual design of the updated detector includes a tracking system, with the Time Projection Chamber (TPC) serving as the primary tracking detector. The TPC offers high spatial resolution (approximately 100 µm over the entire drift length in a 3T magnetic field) in a large 3D volume, which is particularly important for operations at the high-luminosity Z pole (Tera-Z at a 2T magnetic field).
In this talk, we will present the feasibility and current status of using a high-precision TPC as the main tracking detector for electron-positron colliders. The TPC is designed to achieve good separation power, utilizing cluster counting, and we will discuss simulation results for both pad and pixelated TPC technologies for electron-positron colliders. Compared to pad readout in simulations, the high-granularity readout option for the TPC demonstrates better spatial resolution for single electrons, very high detection efficiency, excellent tracking, and superior PID performance (with a resolution of less than 3σ).
We will present the results of track reconstruction performance and dE/dx measurements, review the overall track reconstruction performance, and summarize the next steps toward TPC construction for CEPC physics and the detector Technical Design Report (TDR).
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The Circular Electron Positron Collider (CEPC) and Future Circular Electron Positron Collider (FCCee) have been proposed in recent years as both Higgs factories and high-luminosity Z factories. To meet the demands of Higgs and flavor physics, the tracking system requires high-precision performance, including good spatial resolution, momentum resolution, and particle identification (PID) capabilities.
TPC technology for detection must also achieve a longitudinal time resolution of approximately 100 ns. Additionally, achieving very good separation power through cluster counting is crucial. Simulations and PID resolution studies highlight the potential of TPC technology to extend the capabilities of the Tera-Z at future e+e- colliders.
In this talk, we will present the feasibility and current status of using high-precision TPC as the main tracking detector for e+e- colliders. We will also discuss simulation results of the updated beam background, provided by the MDI group within the CEPC community.
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The Circular Electron Positron Collider (CEPC) is a proposed future Higgs and Z factory. To achieve precise particle trajectory measurement and excellent momentum resolution, the CEPC Inner Tracker will be equipped with sensors that offer high spatial resolution and a low material budget, while remaining cost-effective for a large sensitive area. Novel CMOS-based technologies are being explored for the CEPC Inner Tracker. In this talk, we will present the R&D on these sensor technologies, along with the design of the Inner Tracker for the CEPC TDR. The overall tracker performance and future R&D plans will also be discussed.
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Monolithic Active Pixel Sensors (MAPS) utilizing specialized High Voltage CMOS (HV-CMOS) technology are a promising option for the CEPC inner tracker. By applying a high reverse bias voltage to a highly resistive substrate, a depletion depth of several tens of microns can be achieved, resulting in improved time resolution and enhanced radiation hardness compared to traditional CMOS sensors. Over the past decade, the development of HV-CMOS MAPS has primarily focused on the 180/150 nm process nodes. Transitioning to smaller technology nodes will not only enhance the performance of current designs—including power dissipation, readout speed, and total ionizing dose (TID) resistance—but also introduce more functionalities. To explore HV-CMOS processes with smaller design nodes and meet the requirements of the CEPC inner tracker, a series of chips named "COFFEE" is currently under development. This report will present the design and testing results of COFFEE1 and COFFEE2, along with the latest design plan for COFFEE3.
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Silicon strip detectors are widely used in particle detection. Typically, the signal from each strip is read by a front-end circuit connected to the strip’s read-out pad via bonding wires. We have designed a CMOS Strip Chip (CSC) for the CEPC ITK that integrates a 1024-strip sensor with the front-end CMOS circuitry on the same silicon wafer. The CSC features strips with a pitch of 20 µm and a length of 2 cm. Signals from these strips are transmitted to the CMOS circuit, which includes an amplifier, comparator, buffer, etc. The processed signals are then sent to the back-end circuit. This presentation covers the R&D of the CSC.
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The CMOS strip sensor is a key component of the CEPC Inner Tracker. By extending the Python-based framework RASER (RAdiation SEmiconductoR), we have simulated the complete CMOS Strip Chip (CSC). First, we evaluated its electrical performance, including capacitance, leakage current at operating voltage, and the strip's weighting potential. Next, we simulated the CMOS readout integrated circuit, which includes components such as the amplifier, comparator, and buffer. Finally, we simulated the response of the CSC as a detector using laser and radioactive sources.
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The hit rate study for the CEPC silicon tracking system, induced by beam background processes such as pair production, will impact irradiation, data rates, and the design of the detector, particularly for the CEPC operating in high-luminosity Z-pole mode. In addition to beam properties, the hit rate is influenced by factors such as the distribution of materials near the interaction point, detector materials, sensor granularity, and hit response. This presentation will provide a detailed analysis of the hit rate for the CEPC silicon tracker using simulations with the CEPC software CEPCSW.
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Sub-100nm processes are becoming a critical trend in the development of HV-CMOS pixel detector technology. To evaluate the impact of in-pixel electronics design on HV-CMOS pixel sensor performance at these advanced process nodes, we have designed and submitted a prototype chip named COFFEE2, fabricated using a 55nm HV-CMOS process. This chip features a pixel array of 32 rows by 20 columns, divided into three regions, each with distinct in-pixel amplifier and comparator structures. Additionally, the chip includes a bandgap reference, row/column configurations, and digital-to-analog converters (DACs) integrated into the peripheral circuitry surrounding the pixel matrix. We will present detailed electronic designs, simulation results, and preliminary test results.
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Technology Computer-Aided Design (TCAD) simulations were conducted on High Voltage CMOS (HV-CMOS) sensors with varying substrate resistivities. The simulations investigated how changes in substrate resistivity affect leakage current, breakdown voltage, the depletion region, and the distribution of high electric field areas within the sensor. The effects of pixel gap and p-stop on capacitance were evaluated, with simulation results agreeing with experimental measurements. Furthermore, Allpix2 simulations provided insights into the sensor's response to Minimum Ionizing Particles (MIPs), facilitating an analysis of signal collection and charge sharing phenomena across different substrate resistivities.
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The CEPC plans to utilize a high spatial resolution, low-material, fast-readout, large-area, and cost-effective silicon-based tracker system. CMOS technology is a promising solution. Compared to hybrid silicon pixel sensors, CMOS processes enable smaller sensor sizes while maintaining a lower material budget. CMOS technology is also a potential candidate for future upgrades to other experiments, such as the LHCb Upstream Tracker.
Unlike many CMOS processes that require modifications to achieve sufficient signal generation, commercially available high-resistance wafer-based High Voltage CMOS (HVCMOS) is intrinsically radiation-hard and offers substantial capacitance for signal acquisition. While HVCMOS may have higher noise and power consumption compared to small-electrode CMOS, these factors are manageable for large-area trackers. Recent advancements in the HVCMOS production process at domestic foundries make it commercially customizable.
We will present promising test results from preliminary CMOS sensors, including those from the 55nm process (COFFEE), COFFEE1, and COFFEE2.
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The AC-LGAD technology has been selected for use as the Time-of-Flight (ToF) detector and outer tracker for the Circular Electron-Positron Collider (CEPC). The ToF is crucial for flavor physics at the CEPC, particularly for distinguishing between kaons and pions at low-energy. The AC-LGAD-based ToF and outer tracker will be positioned between the TPC and ECAL, covering an area of 90 m². The expected performance includes a time resolution of 50 ps and a spatial resolution of 10 µm. This talk will present the overall design of the ToF and outer tracker detector for CEPC.
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AC-coupled Low-Gain Avalanche Detectors (AC-LGADs) are designed with a 100% fill factor for high-precision 4D tracking. These detectors have been studied and developed by various institutions, including BNL and FBK. This talk will present simulation and the latest testing results for 50 µm thick AC-LGAD sensors developed by IHEP. We will discuss simulation studies of design parameters and the fabrication process, and demonstrate their impact on sensor performance. The performance of strip-type AC-LGADs will be highlighted, including spatial resolution and timing performance. Sensors tested with a beta source achieved a time resolution of better than 40 ps, which is comparable to standard LGADs with similar gain. Spatial resolution tests conducted using a laser system on sensors with different pad-pitch structures showed a resolution of approximately 8 µm for pad-pitch sizes of 100-150 µm. Finally, we will discuss the new prototype design for the CEPC outer tracker.
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Accurate trajectory measurements and particle identification are crucial for the CEPC's requirements. The CEPC TDR proposes a comprehensive tracking system, including a Vertex Detector, Inner Silicon Tracker, Time Projection Chamber, and Time-of-Flight (ToF) Outer Tracker. This system is designed to deliver superior track position, momentum, and flight time measurements.
The ToF Outer Tracker, using the novel silicon timing sensor AC-LGAD, aims to achieve timing resolutions of a few tens of picoseconds, significantly enhancing particle identification (PID). It also provides position resolution on the order of ~10 micrometers, which improves momentum resolution for high-momentum tracks.
This talk will present the performance of the ToF Outer Tracker based on simulated data from CEPCSW. The performance study will focus on two main aspects: its impact on PID and its effect on tracking momentum measurements. We will also explore the physics potential of several benchmark physics channels enabled by the advanced performance of the ToF Outer Tracker.
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The AC-LGAD technology has been selected for use as the Time-of-Flight (ToF) detector and outer tracker for the Circular Electron-Positron Collider (CEPC). This ToF detector is essential for flavor physics at the CEPC, particularly for distinguishing kaons from pions in the low-energy range. The AC-LGAD-based ToF and outer tracker will be positioned between the TPC and ECAL, covering an area of 90 m².
The geometric model of the LGAD detector has been completed and integrated into CEPCSW. Using the DD4HEP toolkit, this model incorporates all relevant features and aligns with the existing geometry. Calculations have been conducted to assess the hit rate based on the simulation results with the integrated geometry.
POSTER
The Circular Electron-Positron Collider (CEPC) is designed to operate across various center-of-mass energies, offering significant potential in fields where precise Particle Identification (PID) is crucial, such as flavor physics and the study of Higgs boson couplings to light quarks. ToF measurements are essential for PID, particularly in the 1 GeV energy range where the Time Projection Chamber (TPC) alone is not sufficient due to its reliance on energy loss information.
Given the ToF detector's placement ~2 meters from the interaction point and the short lifetimes of charged hadrons, these particles may decay before reaching the sensor. Therefore, it is essential to simulate the ToF detector's acceptance thoroughly. The overall PID performance will be evaluated based on the combined data from the TPC and ToF systems, including detailed studies of their separation power and resolution.
In addition to PID capabilities, ToF measurements are crucial for accurately determining the time of secondary vertices. This is particularly valuable for observing displaced vertices, which are important in searches for long-lived particles. We have developed a basic reconstruction algorithm and calibration process, which will be discussed in this presentation.
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The CEPC plans to deploy a time-of-flight (ToF) detector using AC-LGAD technology to advance its flavor physics research capabilities. AC-LGAD detectors with 100% fill factor, are designed to deliver high-precision measurements of both spatial coordinates and timing for detected particles.
AC-LGADs for CECP will be implemented as strip-type, single-layer structures and will be installed in both the barrel and endcap regions. The sensors in the barrel region will be the longest of their kind globally, while the endcap sensors will feature a non-parallel strip design. IHEP's expertise in LGAD technology will be crucial for optimizing aspects such as radiation hardness, gain layer design, and epitaxial layer growth.
The AC-LGAD-based ToF detector is expected to achieve a time resolution of 50 picoseconds and a spatial resolution of 10 micrometers in the bending direction. Simulation results indicate that this design will greatly enhance the separation of kaons from pions and kaons from protons within the 1-2 GeV energy range. The incorporation of this advanced detector will provide the CEPC with four-dimensional detection capabilities—offering precise timing and positional information for charged particles—thus significantly improving measurement precision and broadening the scope of flavor physics research.
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