Speaker
Boxin Wang
(Institute of High Energy Physics, CAS)
Description
COFFEE3 prototype chip were fabricated with 55-nm HV-CMOS process to aim for the requirements of CEPC inner tracker.COFFEE3 including 4 sectors: 1) passive sensing diode array; 2) standalone PLL block; 3) pixel matrix with in-pixel CSA and half part of discriminator, while other circuits at the end of column; 4) pixel matrix with full in-pixel CSA, discriminator, TDC, while readout circuit at the end of column. The readout out architecture of sect.3 has less cross-talk effect between digital and analog circuit, which is more suitable with the current triple-well HV-CMOS process. The sect.4 could handle higher hit density rate, while need more R&D effector. The current testing results of the first 3 sectors are presented in this poster.
Primary authors
Boxin Wang
(Institute of High Energy Physics, CAS)
Jianchun Wang
(Institute of High Energy Physics, CAS)
Xiaomin Wei
(Northwestern Polytechnical University)
Yang Zhou
(Institute of High Energy Physics, CAS)
Zhiyu Xiang
(Institute of High Energy Physics, CAS)
Cheng Zeng
(Institute of High Energy Physics, CAS)
Leyi Li
(Institute of High Energy Physics, CAS)
Mengke Cai
(Institute of High Energy Physics, CAS)
Weiguo Lu
(Institute of High Energy Physics, CAS)
Xiaoxu Zhang
(Nanjing University)
Yiming Li
(Institute of High Energy Physics, CAS)
Yuman Cai
(IHEP)
Zijun Xu
(Institute of High Energy Physics, CAS)
