Name: The 2025 International Workshop on CEPC abstracts (Silicon Tracker Group)
Start: 2025-11-05T09:00:00+08:00
End: 2025-11-10T11:00:00+08:00
Location: No location set

The 2025 International Workshop on CEPC abstracts (Silicon Tracker Group)

from Wednesday, November 5, 2025 (9:00 AM) to Monday, November 10, 2025 (11:00 AM)

Monday, November 3, 2025
Tuesday, November 4, 2025
Wednesday, November 5, 2025
9:00 AM CEPC Silicon Tracker Detector - Qi YAN (IHEP)
CEPC Silicon Tracker Detector
- Qi YAN (IHEP)
9:00 AM - 9:20 AM
The CEPC Silicon Tracker, comprising the Inner Silicon Tracker (ITK) and Outer Silicon Tracker (OTK), will cover a total active area of approximately 100 m². It integrates advanced pixel sensors for the ITK and microstrip sensors for the OTK, with micron-level precision to achieve per-mille-level momentum resolution, measuring charged-particle trajectories from below 1 GeV/c to above 100 GeV/c. The detector will also serve as a high-precision Time-of-Flight system, targeting a single-layer timing resolution of 50 ps. By combining high-performance sensors, electronics, mechanics, and cooling, the design of the reference detector for the CEPC has been finalized, and the corresponding R&D work is ongoing. This presentation provides a comprehensive overview of the detector design, as well as the current status and future plans for system development. Oral (Qi YAN)
9:20 AM The readout for the silicon Tracker - Xiongbo 严雄波 YAN Xiongbo (高能所)
The readout for the silicon Tracker
- Xiongbo 严雄波 YAN Xiongbo (高能所)
9:20 AM - 9:40 AM
Oral (Electronics Section)
9:40 AM Exploratory Development of 55 nm HV-CMOS Pixel Sensors: Design of the COFFEE Series Chips - Yang 扬 ZHOU 周 (IHEP)
Exploratory Development of 55 nm HV-CMOS Pixel Sensors: Design of the COFFEE Series Chips
- Yang 扬 ZHOU 周 (IHEP)
9:40 AM - 10:00 AM
High-Voltage CMOS (HV-CMOS) pixel detectors, with excellent radiation hardness and fast signal collection enabling nanosecond-level timing and micron-level spatial resolution, are chosen as the baseline for the CEPC Inner Silicon Tracker. Our R&D using a 55 nm process has produced the COFFEE series of prototype chips. Following verification with COFFEE2, the COFFEE3 chip was designed and submitted for tape-out in spring 2025. COFFEE3 implements two readout architectures: one digitizes within each pixel and transmits data in parallel to the array bottom for time stamping, while the other uses a pixel-level Time-to-Digital Converter (TDC) with column-level readout. Both aim for sub-5 ns timing, optimized differently for hit-rate handling and power. This talk will present the COFFEE series R&D, the COFFEE3 design and performance, preliminary test results, and future plans. Oral (Yang ZHOU)
10:00 AM Studies of AC-coupled Low Gain Avalanche Detector for the CEPC Outer Tracker System - Mei Zhao (高能所, IHEP)
Studies of AC-coupled Low Gain Avalanche Detector for the CEPC Outer Tracker System
- Mei Zhao (高能所, IHEP)
10:00 AM - 10:20 AM
AC-coupled Low Gain Avalanche Detectors (AC-LGADs) have become leading contenders for upcoming 4D tracking systems, attracting considerable interest from numerous research organizations. This technology has been selected as the baseline for the CEPC Outer Silicon Tracker (OTK), offering both high-precision spatial resolution (∼10 µm) for momentum measurement and high-precision timing (∼ 50 ps) for particle identification. Research on AC-LGADs developed by the Institute of High Energy Physics (IHEP), featuring 5.65-mm-long strip sensors, has shown impressive results, with a timing resolution of about 40 picoseconds and a spatial resolution of approximately 10 micrometers. Total Ionizing Dose (TID) radiation studies have further indicated that these sensors maintain strong performance under CEPC's radiation conditions. Towards CEPC OTK system, an AC-LGAD with a strip length of ~4 cm has been designed, and its performance be evaluated. This presentation includes simulations of AC-LGAD design parameters, including n+ layer dose, isolation structures and so on, with a focus on capacitance optimization aimed at enhancing performance. The design of IHEP's AC-LGAD strip sensors and the preliminary testing results of AC-LGAD sensors with centimeter long strips will also be reported. Oral (Mei ZHAO)
10:20 AM FPGA-Based Front-End Electronics for AC-LGAD Detector - 丽燕金坤胡 (山东大学)
FPGA-Based Front-End Electronics for AC-LGAD Detector
- 丽燕金
- 坤胡 (山东大学)
10:20 AM - 10:40 AM
The Low Gain Avalanche Detector (LGAD) is a high-precision silicon-based timing detector known for its excellent signal-to-noise ratio and a typical gain of 10–50. The AC-coupled Low Gain Avalanche Detector (AC-LGAD), evolved from the LGAD, represents the latest generation of high-precision 4D detectors capable of simultaneously measuring both the time and position of particles. We proposed a 16-channeal front-end electronics readout electronics (FEE) for AC-LGADs. For analog part, it consisted of a radio-frequency preamplifier and a high-speed discriminator in each channel. All discriminated signals were fed to an FPGA. In the FPGA, 16 channels of time-to-digital converters (TDC) were implemented, based on the tapped delay line (TDL) structure. Test results showed that ~6ps timing resolution for the TDC could be achieved. The FEE system currently provides time-of-arrival (TOA) measurement. High-precision time-over-threshold (TOT) module is under development. With a pulse generator, the intrinsic timing resolution for the FEE is measured. The timing resolution for one channel in the FEE is about 10 ps. The timing resolution for the AC-LGAD detectors with our customized FEE can reach up ~40 ps. The resolution can be further improved after the TOT calibration in the future. Oral (Kun HU)
10:40 AM First RISC-V–Based System-on-Chip for CEPC Readout ASICs - Yuxin Cui (IHEP) 宇鑫崔宇鑫崔 (中国科学院高能物理研究所)
First RISC-V–Based System-on-Chip for CEPC Readout ASICs
- Yuxin Cui (IHEP)
- 宇鑫崔
- 宇鑫崔 (中国科学院高能物理研究所)
10:40 AM - 11:00 AM
High-Energy Physics (HEP) experiments increasingly rely on complex ASICs, driving a growing need for flexible, programmable architectures. We present a RISC-V–based System-on-Chip (SoC) that serves as a versatile control and configuration hub for CEPC ASICs. The SoC integrates tiny_riscv, a lightweight 32-bit processor with a 3-stage pipeline, capable of executing C programs to manage registers and implement communication protocols such as I²C and SPI via firmware. Its application will first be demonstrated in LATRIC, an ASIC for Low-Gain Avalanche Diode (LGAD) readout, with fabrication planned in a 55 nm CMOS process in October. This talk will present the SoC design, its implementation for CEPC ASICs, and prospects for future development and applications. Oral (Electronics Section)
11:00 AM Mechanical Design and Future Prospects for the CEPC Silicon Tracker - 宇杰李
Mechanical Design and Future Prospects for the CEPC Silicon Tracker
- 宇杰李
11:00 AM - 11:20 AM
The CEPC Silicon Tracker (ITK and OTK) will cover a large sensor area of approximately 100 m². Achieving high performance requires minimizing the material budget while ensuring high structural strength and efficient cooling—a particular challenge for this large and sophisticated tracking system. This report presents the detailed mechanical and cooling design of the CEPC silicon tracker detectors, along with the planned R&D toward a prototype detector. Oral (Yujie LI)
11:20 AM A 55 nm HV-CMOS Pixel Sensor Design for High-Energy Particle Tracking with High Hit Rate and Precise Time Resolution - 乐怡李 (中国科学院高能物理研究所（IHEP）)
A 55 nm HV-CMOS Pixel Sensor Design for High-Energy Particle Tracking with High Hit Rate and Precise Time Resolution
- 乐怡李 (中国科学院高能物理研究所（IHEP）)
11:20 AM - 11:40 AM
Poster
11:40 AM A Low-Power 55 nm HV-CMOS Pixel Sensor Readout Architecture for the CEPC Inner Tracker - 丙辰阎
A Low-Power 55 nm HV-CMOS Pixel Sensor Readout Architecture for the CEPC Inner Tracker
- 丙辰阎
11:40 AM - 12:00 PM
Poster
12:00 PM 55 nm HVCMOS Pixel Sensor: Readout Architecture Simulation, Hit Loss Analysis, and Data Transmission Optimization - 晓旭张 (南京大学)
55 nm HVCMOS Pixel Sensor: Readout Architecture Simulation, Hit Loss Analysis, and Data Transmission Optimization
- 晓旭张 (南京大学)
12:00 PM - 12:20 PM
Poster
12:20 PM Current Testing Results of the Sensing Diode, PLL, NMOS Comparator and Readout Circuit of COFFEE3 Pixel MAPS Prototype for CEPC - 博新王 (LHCb)
Current Testing Results of the Sensing Diode, PLL, NMOS Comparator and Readout Circuit of COFFEE3 Pixel MAPS Prototype for CEPC
- 博新王 (LHCb)
12:20 PM - 12:40 PM
Poster
12:40 PM Current Testing Results of the In-Pixel CSA, Discriminator, TDC, and Readout Circuit of COFFEE3 Pixel MAPS Prototype for CEPC - 雨漫蔡 (高能所)
Current Testing Results of the In-Pixel CSA, Discriminator, TDC, and Readout Circuit of COFFEE3 Pixel MAPS Prototype for CEPC
- 雨漫蔡 (高能所)
12:40 PM - 1:00 PM
Poster
1:00 PM TCAD Simulation Study of a Novel AC-LGAD Design with Isolation Structures for Sensor Performance Optimization - 旭黄 (南昌大学)
TCAD Simulation Study of a Novel AC-LGAD Design with Isolation Structures for Sensor Performance Optimization
- 旭黄 (南昌大学)
1:00 PM - 1:20 PM
AC-LGAD (AC-Coupled Low-Gain Avalanche Diode) detector shows great potential for future particle physics and vertex detectors due to their excellent timing resolution and spatial resolution. However, their performance is limited by the sensor's internal capacitance parameters, particularly the bulk capacitance and the inter-strip capacitance. High capacitances of AC-LGAD with centimeter long strips can degrade the signal response speed and increase crosstalk, thereby impairing the timing accuracy and spatial resolution. To address this challenge, this study proposes a novel structural design for AC-LGAD sensors with isolation structures. Through detailed 2D and 3D numerical simulations, we systematically analyzed the suppression effect of the new structure on key capacitance parameters, including bulk capacitance, coupling capacitance, and inter-strip capacitance. The simulation results demonstrate that the new design significantly reduces the overall capacitance. For sensors with this optimization design, we simulate and analyze the charge distribution characteristics of strips as the injection point changes. Based on these results, we further investigated the electrical performance of the sensor: the signal rise time, collected charge performance and the spatial resolution. These results will be discussed in the report. Poster
1:20 PM KNN-Based Position Reconstruction Algorithm for AC-Coupled Low Gain Avalanche Detector - Xiaoxu Zhang (南京大学)
KNN-Based Position Reconstruction Algorithm for AC-Coupled Low Gain Avalanche Detector
- Xiaoxu Zhang (南京大学)
1:20 PM - 1:40 PM
The AC-Coupled Low Gain Avalanche Diodes (AC-LGADs) represent an advanced silicon sensor technology that retains the exceptional time resolution of standard Low Gain Avalanche Diodes (LGADs) while enhancing position sensitivity through their resistive readout structure. This study addresses the position reconstruction challenge in AC-LGADs. Based on a simplified 2D charge diffusion model derived from Ohm’s law and current conservation, the position-dependent signal distributions were simulated for circular, square, and cross-shaped metal pads using MATLAB’s PDE Toolbox, providing scanned datasets. By expanding the feature space and selecting the optimal number of nearest neighbors(K-value), the optimized K-Nearest Neighbors (KNN) algorithm achieved satisfactory reconstruction accuracy on the simulated datasets for circular and square metal pad configurations. Finally, experimental validation was performed using laser-scan data. With neighboring metal pads spaced 3000μm center to center, the optimized KNN algorithm achieved positional Root Mean Square Error (RMSE) of 11.16μm. Poster
Thursday, November 6, 2025
Friday, November 7, 2025
Saturday, November 8, 2025
Sunday, November 9, 2025

Monday, November 10, 2025