5th DRD3 week on Solid State Detectors R&D abstract

29 Jun 2026, 09:00 → 3 Jul 2026, 11:00 Asia/Shanghai

Institute of Space Science & National Institute of Materials Physics (Bucharest, Romania)

Qi YAN (IHEP)

Rehearsal in 9:30 am, June 26, 2026, 多学科楼228

点击链接入会，或添加至会议列表：
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DRD3 conference indico: https://indico.cern.ch/event/1634258/

 

Monday, 29 June

1 Development of Centimeter-Scale AC-LGAD Sensors for Future Collider Timing Trackers

AC-coupled Low-Gain Avalanche Diode (AC-LGAD) detectors have emerged as promising candidates for next-generation particle tracking systems owing to their excellent timing resolution of approximately 50 ps and spatial resolution of about 10 μm. For large-scale tracking detectors at future collider experiments, centimeter-scale strip AC-LGAD sensors are particularly important for reducing the number of readout channels and simplifying system integration. In this work, we present the simulation, design, and tape-out status of a series of AC-LGAD sensors developed at the Institute of High Energy Physics (IHEP), featuring strip lengths ranging from 1 cm to 4 cm. The effects of n+ layer doping concentration on the electrical performance of the sensors are investigated through detailed I-V and C-V simulations. The impact of isolation structures is also studied by comparing device designs with and without isolation implementations. The electrical properties of AC-LGAD sensors with different process parameters and strip geometries are analyzed and discussed. These studies provide guidance for the optimization of large-area AC-LGAD detectors for future high-energy physics experiments.

ACCEPTED ORAL
REHEARSAL

Speaker: Mei Zhao (高能所, IHEP)

2 AC-LGAD Timing Tracker Development for Future Colliders

AC-coupled Low-Gain Avalanche Detectors (AC-LGADs) are a promising 4D silicon detector technology for future high-energy physics collider experiments such as CEPC, offering excellent timing and spatial resolution. This contribution presents recent progress from our team in AC-LGAD sensor R&D, dedicated readout ASIC development (LATRIC), and the establishment of a comprehensive detector testing infrastructure from.
For strip-type AC-LGAD sensors, the design targets a timing resolution of ~40 ps and a spatial resolution of about 10 μm. A systematic study of key device structural parameters has been performed to evaluate their impact on timing performance and position resolution, providing essential input for device optimization and design.
To satisfy the stringent readout requirements of AC-LGAD detectors, a dedicated low-power ASIC, LATRIC, has been developed. The single-channel prototype LATRIC0 has completed functional validation, demonstrating key building blocks including front-end amplification, clock distribution, configuration logic, and data readout. In addition, the 8-channel version LATRIC1 has been fabricated and is evaluated. Joint tests of strip AC-LGAD sensors with LATRIC demonstrate the design of sensor–ASIC system and its combined performance.
A dedicated characterization infrastructure has been established, including a laser TCT scanning system and a ⁹⁰Sr β-source test setup, with beam test preparations in progress.
These developments provide a solid basis for the realization of large-area, high-precision 4D silicon tracking systems for future collider experiments.

ACCEPTED ORAL
REHEARSAL

Speaker: JiaJian TEOH 张嘉健 (IHEP)

DRD3_AC-LGAD_30June2026.pdf

3 Development of the SICAR 4H-SiC Radiation Detector

This abstract reports on the design, fabrication, and characterization of the SICAR 3 4H SiC low gain avalanche detector (LGAD) implemented on a 350 nm SiC MOSFET process platform. Unlike previous SICAR 1 and SICAR 2 generations that relied on epitaxy defined structures, the SICAR 3 device employs an ion implantation based process to form the gain layer, junction termination extension (JTE), and p⁺⁺ contact layer. The edge termination is realized with a JTE assisted field plate, replacing the earlier mesa plus field plate design. PIN diodes, Schottky diodes, and LGADs were fabricated on the same wafer, which consists of a low resistivity p type 4H SiC substrate, a 70 μm thick N⁻ epitaxial layer (1×10¹⁴ cm⁻³), and implanted regions activated above 1500 ℃. Electrical characterization shows that the selected LGAD device has a higher reverse leakage current (approximately 10⁻⁵ A at 1000 V) than the PIN device (approximately 10⁻⁹ A). Capacitance–voltage measurements reveal a distinct gain layer depletion feature at 120–130 V. Charge collection measurements using a ⁹⁰Sr source demonstrate that, relative to the PIN reference device, the LGAD achieves a charge gain of approximately 10 at high reverse bias. Preliminary timing measurements, after subtracting the reference contribution, yield a detector time resolution of 60 ± 5 ps at a reverse bias of 400 V. These results verify the basic feasibility of forming a 4H SiC LGAD multiplication structure by MOSFET process platform.

ACCEPTED ORAL
REHEARSAL

Speaker: Xiyuan 希 媛 Zhang 张