1. some news from MALTA chip that was reported at the TWEPP meeting was delivered. The power density of the analog part is 75mW/cm2(1uW/pixel), with a pixel size of 36um*36um, time walk 25ns@400e-, while our current design is 138mW/cm2(0.8uW/pixel), with a pixel size of 25um*25um. These two power density seems agrees with each other, however, MALTA(and other similar chips) achieves faster time walk of 25ns(same with BX) at the same power density. Therefore we should find out a reason or solution for this issue.
2. progress of the digital cell was reported. Fast-or logic was added and different configurations of the fast-or grouping was simulated. Preliminary bus delay was simulated, however, only gate delay was considered. Next step, bus load with parasitic R and C will be added for a more precise estimation.
3. Preliminary calculation of the periphery power dissipation was given, based on ALPIDE. However it did not agree with similar chips running at similar conditions (MALTA 10mW/cm2, MONOPIX 68mW/cm2). Further analysis with real load and real time sequence should be done for a precise estimation, and more ref design information can be found from MONOPIX chip.
4. NWPU will send detailed requirements for design input (pixel array and trigger) to the corresponding persons. Preliminary design will soon be given for a combined simulation and verification.