1.Tianya reported the progress of the digital cell design. The shift register chain for the slow control was added and simulated. Comments were: when simulated the long chain, the RC load of the bus should be considered, otherwise the setup timing of the shift chain might not be satisfied. Average current of the digital cell was further evaluated.
2.No new progress of other parts. For periphery logic and NWPU, please send the necessary requirements asap and preliminary designs, so that the initial simulation of the full matrix can performed.
3.Design requirements for LDO and DACs were discussed again. For LDO, the output ability should cover a power dissipation of 100~200mW, core voltage of 1.8V, load cap <1nF. For DACs, the load cap is more or less several tens of pF. It can be configured by SPI interface.
4.Some considerations from Weiguo were discussed related to the process configuration.