1. Wei Wei reported some possible modifications to simplify the existing design. The idea is to eliminate the duplicate logic in both pixel digital logic and address encoder, leave one set in only one place. 4 schemes were discussed and compared. 2 of them were most likely to become the final candidates: scheme 1 kept most of the design from ALPIDE, and scheme 2c were similar with FE-I3. We may do some parallel design in the first tapeout based on these two schemes.
2. Scheme 2a are the mix of FE-I3 and ALPIDE, still need to be decided if it is included in the current design after finishing the other two schemes. There seems no obvious advantage of scheme 2b, we just passed it.
3. Zhang Ying reported the progress of the pixel analog design. Now the time walk can be within 25ns (~22ns) @440nA, and the simulated noise by S-curve is ~6e, with a threshold of 172e. More results from Monte-carlo simulation are coming.
4. The pre-final design of the three parts: pixel analog, pixel digital, and periphery should be collected asap. Then the combined simulation can start.
5. Xiaoting reported that the current highest frequency of the VCO can be higher than 2.56Gbps at the worst case, after solving some bugs.