Powered by Indico v3.0.3
1. Xiaomin talked about the slow control scheme for the pixel array. The SPI config data stream will be distributed into 512 double column from the periphery in the test mode, while the load signal will only be fanned out into every double column. Each double column will have only one chain of config data, not two chains. The config clock will also be given from the periphery, that every 512 clock of the SPI will generate one pulse to the double column.
2. DAC dynamic range was discussed, and without a big issue. DNL/INL of the DAC was not important for biasing. However, we agreed the bias net for the sensing diode should be provide from external, and should be precisely tunable.
3. Tianya will prepare the talk for the CEPC workshop and will make a rehearsal in advance.
4. We propose to have a chip design review on April 22~30 before the chip tapeout.
5. Zhijun asked if the threshold triming DAC can be added for the pixel. The main issue is that DAC will occupy a large area. If the pixel size can be stretched in one dimension, it should be possible.