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1. Zhang Ying reported some simulation results as the feedback to the review questions.
i. for the time walk, Monte-carlo simulation was done at the minimum input at 300e-, and the big signal at 3000e-. There will be further timing error added due to the deviation of output delays. The STD was about 1.06ns, and 200ps respectively. Although we didn't have agreement of how to define the final time walk, it shows the timing error is indeed enlarged.
ii. threshold variation due to the detector capacitance was also simulated. It showed that the detector capacitance indeed will affect the threshold non-uniformity, however this capacitance comes from the active layers and very hard to estimate. It may be possible to test from the MIC4 chip and see the threshold distribution for estimation.
2. Wei Xiaomin was thinking to add some test features to the periphery;
Weiguo Lu reported some verification simulation results. One bug was found from the array SPI connection, and has already discussed with Tianya.
The ALPIDE-like pixel array is still fighting for the AERD super-pixel logic, at the 128-pixel level.
Xiaoting Li will soon finish the serializer layout.
3. We propose to move our weekly meeting from every Monday to every Thursday, because of the new schedule of some colleagues.
4. We agreed to fully finish our chip layout before May 20th.