MOST2 chip design meeting

Tuesday 11 Jun 2019, 08:00 → 18:00 Asia/Shanghai

1. The interface between the ASIC & test board were discussed.

  2. We proposed to design two test boards, one to test the main chip, and the other one to test the PLL and LDO blocks. The test setup will based on daughter board + KC705 FPGA Evaluation board, two boards will be connected by FMC socket and probably an extension board.

  3. We discussed the interface pin by pin, currently only LDOs, DAC, and buffers are need on the daughter board.

  4. We propose to consider the possible improvement for the next version, and initiate the following designs soon.

  5. We also propose to collect all the nominations of the chip name and make a vote by the next week.

 

1 pin list discussion for test board

Slides MOST2_TP1_PINLIST.xlsx