1. Tianya gave some simulation results on power dissipation. For both FE-I3 and ALPIDE scheme, the average current in the initial stage is high, and will go up when there is no hit. The reason for why the FE-I3 scheme the current will also go up, is to be understood. The situation when there are random hits every 8.3us was also studied. The current of FE-I3 scheme is higher than ALPIDE because the peak current is larger due to the address encoder. The dynamic latch was also simulated, and the results will be discussed next week with Xiaomin.
2. We had a discussion with Joao on the recent plan. The next critical goal is to submit the chip before the mid-term review in May, 2020. In order to keep up the schedule, we should aim at finishing the 2nd chip design before December, and to submit the chip by the end of this year.
We should prepare enough test boards also for other collaborators for evaluation, and make sure the functionality is correct before delivering.