MOST2 chip design meeting

Monday 26 Aug 2019, 08:00 → 18:00 Asia/Shanghai

  1. Wei Wei gave some simulation results based on the behavior level model for the purpose to shift the data sampling time from +25ns of the "read" signal, to the +37.5ns of the "read" signal. The simulation showed that this gave a larger headroom for the timing. Xiaomin suggested that the simulation base on more real circuit, and the "read" signal should also be widen to 37.5ns. Also, we can consider to package the pixel array, so that for the periphery, all the data are synchronized with the clock. Therefore we can also consider to add latches at the EOC.

  2. We discussed again based on Tianya's simulation results for the dynamic latches. The conclusion was that, the quiesent average current rather than the current during the shift loading phase, is more interested for us,including both 0->1, and 1->0 conditions. That means the shift clock should be down. Also we should make sure the latches can keep the held state and will not go back to the high-z state, which will make the average current very large.

  3. The test PCB is going for the contract this week, and will be produced within 10 workdays after the payment.

  4. We also discussed the abstract submission for the HIROSHIMA meeting in December.