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1. Tianya reported some simulation results.
It seems the for the FE-I3 address encoder, high-z state still existed when no hit was generated. It will thus increase the power consumption. We should further check where the problem came from, and see if we should add pull-up resistor to avoid this state.
For the pixel-latch, it seems that the current will be high when data is loading from 0->1， and the current will be about 4us. It will be dangerous because multiple pixel will be loaded together. We should first check again if it is really a problem, and then to see how to modify the latch for a more saver design.
2. Wei Wei reported the simulation results according to the discussion last week. Real pixels were used for the simulation, and a latch was added for each address output at the EOC. The proposed scheme that to latch data at 1.5clk still work. Only a read signal as the original scheme, and a new read-latch signal which is delayed by 0.5clk from the read are needed.
3. We have 3 abstracts submitted to the Hiroshima conference, the pixel-array design by Zhang Ying, the periphery design by Xiaomin, and DAC by Zhang Liang.
4. Requirements for the test boards were collected last week, and SDU is going to order the necessary chips and components.