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1. During the test of TaichuPix1, we detected some short problems between the VDD net and VSS net. It was due to the soft connect error on the padrings. However, when forcely powered up to 1.8V, the chip showed signs of correct functionality. The test block of PLL was tested, showing the PLL can be locked correctly at 40MHz input frequency, meaning the VCO frequency can go to 2.24GHz, and the maximum frequency it can achieve was tested to be 2.912GHz.
2. The next step is to connect the test board with FPGA EVA board, and to see if the chip can still be correctly controlled by FPGA.
3. To shrink the area of the periphery, a SRAM IP was tried. However, the provided size was too large and not suitable for array floorplan. Other solutions will be studied. Xiaomin also proposed to provide a pull-up signal, that is one clock delayed from FASTOR, for a larger safety room for the pull-up transistor.