MOST2 chip design meeting

Monday 23 Dec 2019, 08:00 → 18:00 Asia/Shanghai

1. Tianya reported design status of the pixel digital. Both FE-I3 and ALPIDE schemes were simulated with the proposed modifications: the pull-up transistor, the address latches, and the read-latch shift on the timing sequence. The power consumption of the pixel digital was also simulated, the peak power consumption was about 76~100mW/cm2, while the average power was only 3mW/cm2, which was smaller than what was thought.

     He also gave a preliminary simulation result for the proposed super-pixel scheme based on the FE-I3 scheme. It showed that the scheme functionally worked.

  2. A discussion was made for the next tapeout in February 2020. The submission date will be Feb. 10, and the major goal is to have a fully functional chip with all blocks integrated. The dimension of the pixel array, the proposed functional to be newly added and tested, and other possible improvement was discussed.

     We will make a detailed proposal for the tapeout next week, with everyone's detailed schedule. 

Digital Pixels 20'

slides digital_pixel_V2_20191223.pdf