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1. Tianya reported the test status of Tcpx1. The scanned scurve was fitted and the ENC was given by the simulated value of the injection capacitor.
2. Wei Wei proposed the recent schedule of the chip design. We will prepare for the full size chip tapeout before April. TID test and beta source should be proceeded in parallel to verify the pixel analog cell. The major design task is the pixel array rescaling to 1024*512， while the detected bugs should be solved.
At meanwhile we should find help and push the related paperwork for the bidding for both IFAE & IHEP. We should also make clear the cost of the full size tapeout and the process solution.
3. A new test board was designed and submitted to make a more compact connection towards the FPGA Eva board.