MOST2 chip design meeting

Asia/Shanghai

  1. Wei Wei reported the TID test status for Tcpx2. The chip was exposed in the synchrotron radiation. The dose rate was calibrated by a iron chamber first and the dose rate was set to be about 300rad/s. The chip was fully powered up with correct bias and system clock. It survived after 2.5Mrad, the functionality was normal and the performance was in good region. The dose was further accumulated to 30Mrad, and the chip still worked fine. The two candidate design of the pixel analog circuit didn't show large difference towards the radiation. To make the final decision of the pixel cell, we still need the beta source results to see the efficiency.

  2. Tianya reported the test status of Tcpx1 chip. The analog part showed different performance at different bias condition. It was suggested more pixels to test so that the threshold dispersion can be tested, besides the noise test. The image results between the SPI readout and LVDS readout were also compared.

  3. Zhang Ying reported the test status of Tcpx2 chip. S1-S4 sectors showed different performance at the same bias condition. The noise and threshold dispersion were tested by Scurve scan while one entire column was enabled during each test. It seemed S1 had the minimum threshold, the minimum threshold dispersion, while the ENC was the maximum. The S3 had the minimum ENC, while the threshold and the dispersion were higher. However, we should consider the dispersion also as part of the system noise. Also, we will test more chip to see the distribution in multiple chips.

     The chip was also tested at the minus substrate voltage. The bias condition has to be tuned at different substrate voltage. The chip is recoverable when supplied with minus voltage, while some phenomena can be observed and to be understood. More chips are also to be tested.

  4. Xiaomin reported a proposal for the data link improvement with JESD204B. However, it requires the serializer to be modified from 32 bits into 40 bits. It requires a big design modification for the Serializer architecture and will introduce a big risk. We decided not to make the the change if the next version is the full size tapeout.

     We also discussed the layout size. It seemed very difficult to make the pixel cell 1um smaller in the X dimension. Therefore the column pitch has to be still 25um.

  5. The new test board was said to be ready by the end of this month. However due to the following vacation, the soldering can only be done after the Spring Festival. 

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