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1. Raimon reported some status from the TJ process evaluation. We still wait for the response from TJ for the pixel cell evaluation.
2. Tianya reported the trigger setup and test in the Tcpx1. Trigger latency was decided by the tunable delay of APULSE and Trigger sent from the FPGA, and it was defined to be 13us. Then it was used for the setup when a scintillator was used as the trigger source. The hitmap obtained by using the trigger functional was found much more efficient than triggerless, and the cluster size was preliminarily measured then. The measured cluster size was promising, however it still needs explanation that why the trigger latency of 13us is much larger than the maximum FIFO depth of 6.4us.
3. Wei Wei reported the full size chip design status. The LVS was OK with all the blocks integrated. Extra top pads and top power connections were added to help with the power supply, while they were still scribe-able to leave the rest of the chip with the necessary ladder assembly features. IO pads floorplan was also sent for the flex cable design evaluation.
4. Zhang Liang reported the modified version of DAC for the full size chip. The detected problems with large leakage current, and the non-linear behavior of the transfer curve were solved by the modified design. It was also switchable between the modified version and the old version by configuration bits.
5. Xiaomin reported the possibilities to serial connect the SPI bus between chips in order to save the routing space in the flex design. Technically the functional works, however we need further discussion concerning the system reliably when a chip fails in the multiple chip chain on the ladder. We must not let the rest of the chips fail altogether.
6. We also had a discussion about the LDO block test consideration. It will be tested independently as a single chip. The test board will also be independent from the main chip while not to affect the main chip functionality.