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Test of a prototype Topmetal chip for N𝜈DEx experiment

Aug 11, 2022, 2:56 PM
2m

Speakers

Dongliang Zhang (Central China Normal University) Hulin Wang (Central China Normal University) Kai Chen (Central China Normal University) Tianyu Liang (Central China Normal University) jun liu (Central China Normal University)

Description

N$\nu$DEx is a recently proposed experiment to search for the neutrinoless double beta decay of $\mathrm{^{82}Se}$ with high pressure $\mathrm{SeF_{6}}$ gas TPC. The readout plane made of Topmetal-S chips is the key to achieve the desired 1\% FWHM energy resolution.
Two versions of the Topmetal-S chips, featuring the capability of direct ion charge detection without avalanche gain, have been designed and fabricated.
The design of both versions' chip will be presented. And the characterization results, which were tested by injecting pulses and radiation source, as well as the test system will also be described.

Summary

Neutrinoless double beta decay experiment(0$\nu \beta \beta$) is crucial to understand the property of neutrino, especially for its mass and Majorana/Dirac nature. N$\nu$DEx (No Neutrino Double-beta-decay Experiment) is a 0$\nu \beta \beta$ search project using a high pressure $\mathrm{SeF_{6}}$ gas time project chamber (TPC) in China JinPing underground Lab. $\mathrm{SeF_{6}}$ has high electron affinity. There is virtually no free electron drifting in it. So the ions need to be directly collected without charge multiplication. The Topmetal-S chip, with its topmost metal for charge sensing, is designed for this purpose. To achieve the 1\% FWHM energy resolution while keeping a good tracking performance, the equivalent noise charge (ENC) of the topmetal-S chip is desired to be at <30 e level. More discussion about the advantage of using CMOS integrated sensors in 0$\nu \beta \beta$ can be found in arXiv:2010.09226. The charge collected by the sensor of chip will be converted into voltage signal by charge sensitivity pre-amplifier (CSA) inside the chip. Six bias voltages in CSA are adjustable to allow fine tuning the work states of the CMOS transistors. So far two versions of the Topmetal-S chips have been designed and fabricated. The first version of the Topmetal-S is fabricated using X-FAB 350~nm technology. The charge collection capability is confirmed. Two methods are used to measure the ENC. 1) Charge injection through pulse signals on the guard-ring. The amount of charge injected could be estimated using the capacitance of the guard-ring and the amplitude of the pulse. A new method is developed to precisely determine the capacitance of the guard-ring. The measured value is substantially different from the value extracted from the EDA software. 2) Using the 5.5~MeV $\alpha$ and 59.5~keV, 26~keV $\gamma$ rays from $^{241}\mathrm{Am}$ decay. A small TPC using P10 gas is built for this test. The amount of charge induced by these radioactive rays could be calculated from their energies and the $W$ value of P10 gas. Both methods show consistent results that the ENC of the first version Topmetal-S is in the range of 500-600 e$^{-}$, which is much larger than the design value. Further study shows that the CSA inside the chip is unstable and its open loop gain could not reach the designed value due to a defect in the design. The second version of the Topmetal-S chip, fabricated using GSMC 130~nm technology, is developed to address the issues found in the first version. The characterization of the second version is on-going and the results will be presented at the conference. Further improvements and integration of other modules (e.g., network readout) is planed in the future versions. A final fully functioning version is expected to be ready in 2025 along with the road-map of N$\nu$DEx experiment.

Primary authors

Dongliang Zhang (Central China Normal University) Hulin Wang (Central China Normal University) Tianyu Liang (Central China Normal University)

Co-authors

Kai Chen (Central China Normal University) jun liu (Central China Normal University)

Presentation materials