The 2024 International Workshop on CEPC abstracts

Session

Inner Silicon Tracker (ITK)

23 Oct 2024, 13:00

Contribution list Timetable

13. CEPC Inner Silicon Tracker (ITK) Towards the TDR

Yiming 一鸣 Li 李 (IHEP)

23/10/2024, 13:00

The Circular Electron Positron Collider (CEPC) is a proposed future Higgs and Z factory. To achieve precise particle trajectory measurement and excellent momentum resolution, the CEPC Inner Tracker will be equipped with sensors that offer high spatial resolution and a low material budget, while remaining cost-effective for a large sensitive area. Novel CMOS-based technologies are being...

14. HVCMOS Pixels R&D for CEPC ITK

Yang ZHOU (IHEP)

23/10/2024, 13:20

Monolithic Active Pixel Sensors (MAPS) utilizing specialized High Voltage CMOS (HV-CMOS) technology are a promising option for the CEPC inner tracker. By applying a high reverse bias voltage to a highly resistive substrate, a depletion depth of several tens of microns can be achieved, resulting in improved time resolution and enhanced radiation hardness compared to traditional CMOS sensors....

15. CMOS Strip Chip Design for CEPC ITK

Xin Shi (IHEP)

23/10/2024, 13:40

Silicon strip detectors are widely used in particle detection. Typically, the signal from each strip is read by a front-end circuit connected to the strip’s read-out pad via bonding wires. We have designed a CMOS Strip Chip (CSC) for the CEPC ITK that integrates a 1024-strip sensor with the front-end CMOS circuitry on the same silicon wafer. The CSC features strips with a pitch of 20 µm and a...

16. CMOS Strip Chip Simulation with RASER

森 赵

23/10/2024, 14:00

The CMOS strip sensor is a key component of the CEPC Inner Tracker. By extending the Python-based framework RASER (RAdiation SEmiconductoR), we have simulated the complete CMOS Strip Chip (CSC). First, we evaluated its electrical performance, including capacitance, leakage current at operating voltage, and the strip's weighting potential. Next, we simulated the CMOS readout integrated circuit,...

26. Beam Background Study for the CEPC Silicon Tracker

Zhan Li (IHEP)

23/10/2024, 14:20

The hit rate study for the CEPC silicon tracking system, induced by beam background processes such as pair production, will impact irradiation, data rates, and the design of the detector, particularly for the CEPC operating in high-luminosity Z-pole mode. In addition to beam properties, the hit rate is influenced by factors such as the distribution of materials near the interaction point,...

18. HVCMOS (COFFEE2) Design

乐怡 李 (中国科学院高能物理研究所（IHEP）)

23/10/2024, 14:40

Sub-100nm processes are becoming a critical trend in the development of HV-CMOS pixel detector technology. To evaluate the impact of in-pixel electronics design on HV-CMOS pixel sensor performance at these advanced process nodes, we have designed and submitted a prototype chip named COFFEE2, fabricated using a 55nm HV-CMOS process. This chip features a pixel array of 32 rows by 20 columns,...

19. HVCMOS (COFFEE) Simulation

Jianpeng Deng (Zhejiang University)

23/10/2024, 15:00

Technology Computer-Aided Design (TCAD) simulations were conducted on High Voltage CMOS (HV-CMOS) sensors with varying substrate resistivities. The simulations investigated how changes in substrate resistivity affect leakage current, breakdown voltage, the depletion region, and the distribution of high electric field areas within the sensor. The effects of pixel gap and p-stop on capacitance...

17. HVCMOS (COFFEE) Testing

Zhiyu Xiang

23/10/2024, 15:20

The CEPC plans to utilize a high spatial resolution, low-material, fast-readout, large-area, and cost-effective silicon-based tracker system. CMOS technology is a promising solution. Compared to hybrid silicon pixel sensors, CMOS processes enable smaller sensor sizes while maintaining a lower material budget. CMOS technology is also a potential candidate for future upgrades to other...