Speaker
Description
The Circular Electron–Positron Collider (CEPC) will pursue a broad physics program by operating at several center-of-mass energies and luminosity levels, including Higgs, Z, and W-pair modes. This range of operating points places diverse requirements on the detector and its trigger and data acquisition (TDAQ) system. The trigger system is organized into two levels: a Level-1 (L1) trigger for real-time hardware-based event selection and a High-Level Trigger (HLT) for subsequent event processing. At the heart of the L1 system is the trigger data-processing module, which must handle data from multiple sub-trigger systems while meeting stringent requirements on throughput, latency, and flexibility. I. These requirements motivate the development of a shared and adaptable processing platform.To address this need, we have developed a common trigger data-processing module intended for use across the CEPC sub-trigger systems. By sharing a common hardware platform, the design aims to streamline development, integration, operation, and maintenance while allowing the same module to be adapted to different trigger applications. The module is implemented in the Advanced Telecommunications Computing Architecture (ATCA) form factor and is centered on an AMD Virtex UltraScale+ field-programmable gate array (FPGA). Eleven Quad Small Form-factor Pluggable (QSFP) modules provide 44 high-speed lanes, each supporting data rates of up to 25 Gb/s. The module also incorporates 16 GB of Double Data Rate (DDR) memory to support temporary event buffering for hundreds of milliseconds, together with an Intelligent Platform Management Controller (IPMC) and a K26 system-on-module (SOM) for board-level management and control. To date, a series of board-level functional tests has been carried out on the prototype module, covering the on-board power supply and distribution subsystem, clock distribution, FPGA configuration ,gigabits transceiver(GT) links, and DDR. The results obtained from these tests are consistent with the expected behavior of the corresponding subsystems. Testing of the K26 SOM-related functionality remains ongoing . Together, the module design and the completed tests provide a common hardware foundation for future L1 trigger-firmware integration, system-level verification, and adaptation to the requirements of different CEPC sub-trigger systems and operating modes.
