Speaker
Description
Monolithic Active Pixel Sensors (MAPS) in advanced CMOS nodes must balance timing, power, and noise for next-generation tracking detectors. For the CEPC Inner Tracker, the system-level requirements are a timing resolution of ~3 ns and power consumption below 150 mW/cm². Within this power budget, the analog front-end (AFE) consumes the largest fraction, making its optimization the most effective path toward meeting the overall system target. In a domestic 55nm HV-MAPS process, the sensor's deep-well configuration (VDNW/DPW) introduces significant parasitic capacitance (Cw) that dominates the front-end load, directly limiting the AFE noise and power efficiency. This work presents a design-side co-optimization framework based on an FAB-provided baseline process. A TCAD model is built and calibrated to decompose the sensor capacitance into its components (Cd vs. Cw). The front-end amplifier is then optimized using a gm/ID methodology under the extracted capacitance load. A 3×3 pixels TCAD electric-field data is imported into Allpix2 for signal collection simulation, enabling iterative feedback to the layout design. This work establishes a practical design flow for sensor-AFE co-optimization, providing a reusable foundation for the CEPC ITK pixel chip development.
