1. IE browser is NOT supported anymore. Please use Chrome, Firefox or Edge instead.
2. If you are a new user, please register to get an IHEP SSO account through https://login.ihep.ac.cn/registlight.jsp Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
4. The max file size allowed for upload is 100 Mb.
21–26 Oct 2026
Sheraton Shanghai Jiading Hotel
Asia/Shanghai timezone

Modeling and Simulation of Column-Drain Readout for AGORA Vertex Detector Pixel Sensors

Not scheduled
20m
Junior Ballroom III

Junior Ballroom III

Oral Presentation 07: Silicon Detectors Silicon Detectors

Speaker

Mr Han Yu (Institute of High Energy Physics of the Chinese Academy of Sciences)

Description

The Circular Electron Positron Collider (CEPC) aims to test the Standard Model and search for new physics through precision measurements of electroweak, Higgs, and heavy-flavour processes. CEPC plans high-luminosity operation at energies relevant to Higgs, W, and Z boson production, with an expected physics event rate of the order of 100 kHz at the Z pole. Under these conditions, beam-induced backgrounds can produce local hit rates of approximately 100 MHz/cm² in the innermost vertex detector layers. This sustained high hit load requires fast hit acquisition and readout to minimize readout dead time and data loss.
AGORA is a detector concept being developed for CEPC and FCC-ee, with its vertex detector supporting heavy-flavour identification and precision physics measurements. To meet these requirements, its pixel-array readout scheme must process data rapidly and reliably within a limited power budget. Achievable readout performance is constrained by pixel response times, control-signal propagation, and address delivery. These delays affect the coordination of successive readout operations and limit processing speed, motivating a realistic timing description at the architecture design stage.
This work presents a parameterized pixel-array delay model implemented in Verilog for a column-drain readout architecture, supporting the design and validation of digital readout schemes for the AGORA vertex detector. The model incorporates circuit propagation delays into hit storage, readout control, and address transmission. It enables timing studies under different configurations and hit conditions to identify potential readout timing conflicts early in the design process and assess the feasibility of candidate schemes under nonideal timing conditions. Basic functionality has been verified through simulations of isolated hits, priority-ordered multiple-hit readout, and retention of new hits in previously unhit pixels during readout freezes.
This contribution will present the delay modeling approach and representative timing results for AGORA vertex detector readout validation. In particular, it will discuss the effects of pixel response times and signal propagation delays on readout timing, together with the application of the model to identifying potential timing conflicts and validating candidate readout schemes.

Primary authors

Mr Han Yu (Institute of High Energy Physics of the Chinese Academy of Sciences) Ms Tong Li (Nanchang University) Prof. Xiaomin Wei (Northwestern Polytechnical University) Prof. Tianya Wu (Nanchang University) Prof. Yunpeng Lu (Institute of High Energy Physics of the Chinese Academy of Sciences)

Presentation materials

There are no materials yet.