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Description
The pixel density of the front-end detectors continues to rise, and with it the power they consume—now stretching into the watt range—while the cable mass and thermal budget of the detector volume remain essentially fixed. Today's arrays are powered in parallel at low voltage and high current (roughly 2 V/24 A), a scheme that already strains the cable budget and the associated I²R losses. This work moves to serial (constant-current) powering: a single input of 48 V/1 A uses high voltage and low current to cut cable losses, which is especially attractive in the strong solenoid field and under a strict noise budget. Serial powering removes the cable problem but brings its own set of challenges: shunt-branch dissipation, an uncontrolled open circuit that can take down the whole chain, a floating local ground with no shared reference, and added noise. These are precisely the difficulties already encountered in the ATLAS serial-powering schemes.
Candidate conversion topologies are reviewed and compared: buck DC-DC, switched-capacitor, shunt LDO, and hybrid combinations. A buck is efficient at a small step-down ratio, but its switching-node parasitics grow as the ratio increases, and magnetic-core inductors do not survive the field; small air-core parts remain a workable fallback. Switched-capacitor converters are compact and fixed-ratio, but they are inefficient at large conversion ratios and need many capacitors and high switching frequencies. Two hybrid approaches are proposed. The first is a delta-modulated switched-capacitor stage followed by an LDO: it needs no inductor, operates in series, and reaches about 80% efficiency at roughly 500 µV ripple, though redundancy and the LDO dropout limit its transient response. Replacing that stage by a switching constant-current capacitor, a hybrid buck, and an ultra-low-dropout LDO requires only a small air-core inductor (~0.5–1 µH), reaches above 90% at about 100 µV ripple, and trades current margin for voltage margin, giving good short-burst response without sacrificing efficiency.
A 1.1 A four-stage simulation, with 1.8 V and 1 A per stage and a 60 dB LDO gain, is used to model the rail build-up, constant-current capacitor charging, and final LDO settling. Two demo boards confirm the concept in hardware, including a version built around an 80 V/10 A GaN power stage, a 1 MHz buck with an 8 A NMOS, and a 1.5 A LDO with 150 mV dropout. Results show a stable serial chain settling to a 3.3 V rail and successful cascaded charging.
Three key issues specific to serial powering are addressed. Because the reference ground floats along the chain, the HV MAPS substrate, which must be back-biased to −70 V to fully deplete the bulk (versus about −6 V in conventional MAPS), requires each die to generate its own independent bias voltage for collection efficiency; the simulation confirms a monotonic bias from −70 V to −58 V across five dies while keeping the local substrate voltage constant. To survive an open circuit, DTI isolation separates three independent voltage domains (pixel/power, bias generation, and inter-stage detection), so that a stage can be shorted locally through a redundant path before it trips on over-voltage, keeping the chain current stable. Finally, spread-spectrum suppression lowers the EMI peaks introduced by switching. For data transport across the floating ground, an AC-coupled LVDS link provides a ground-fault-tolerant serializer channel, and transmission is gated off during power-rail switching, occupying less than 1% of the transmission time to secure signal stability.
Future work integrates the hybrid buck with inter-stage coordination to raise transfer efficiency, adds the ultra-low-dropout LDO and open-circuit monitoring, evaluates noise levels and sources, and considers radiation effects and radiation hardening.
