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1. Tianya gave some slides about the digital cell design status.
The simulation of the logic function was the same as behavior model. Some problems of co-simulation was encountered, and will be checked later.
The area of the current logic was estimated without routing, seems in the same level as existing ALPIDE.
Further consideration of address encoder logic will be taken.
2. Xiaomin proposed some issues about the interface for discussion.
2.1 The delay of the address valid to the READ, and the delay of the FASTOR clearance to the READ, should be less than 12.5ns, and 50ns respectively. considering the chip has ~500 rows, these seemed to be really issues. Tianya will evaluate the situation.
some rough estimation was that both of these issues may not be fatal. The FASTOR logic has to be grouped, or with superior connections to speed up the propagation. The backup solution for READ is the possibility to use 2 positive cycles and 1 negative cycle within its 2-clk-long period.
2.2 In reality, the column-FIFO cannot be actually implemented for each individual column, since 25um width is too narrow. More reasonable case is the "super" column-FIFO shared by several columns. This may leads to a longer deadtime for each column. We need a simulation about "the column dead time vs trigger loss", so as to decide the worst case.
3. Zhijun showed some slides on how the trigger latency was decided. Yet it is a full detector scale topic, and hard to have any decision so far.