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1. the solutions for the reported bugs (repeatedly readout pixels) were discussed. Both the edge detection and edge sensitive (DFF based) algorithm worked. Remained questions for the solution were:
1.1 Was 0.5ns delay enough in the real situation? One issue is the pixel noise, will it cause some glitches that lead to multiple detections? The other issue is related to the Corner simulation. In the worst case, will the 0.5ns become too short (say 0.2ns for example) to be detected by the logic gate? These need further simulation.
1.2 Area occupation. The delay cell seems to be large (similar as a DFF). Can we put this cell within the current pixel area?
2. Tianya estimated the pixel digital area. The problem is by using standard digital library, it seems impossible to integrate current logic into the pixel cell (25um by 25um). The former design from MIC4 used full customized digital cells and layout. By doing so, a simulation based on the final cells should be ensured.
3. simulation result for the proposed question - READ when low, was discussed. By current design of AERD, the address code will be held during READ is low, therefore there is no problem for the READ-low. The next step is to make sure if 2clks works for the TDA 40ns case, or we have to allocate 3 clks for each hit.
4. Some further questions were proposed related to the current address encoder design:
4.1 Before the cell was set, the output of the AERD cell is ~700mV, which will result some problem for the EOC logic. One possible solution is to read every pixel by calibration injection, during the power-up configuration phase. Once the pixel was read (address encoder was activated), its output will be held and thus the output level is well defined.
4.2 Now the AERD design seems to be based on dynamic logic. Although in a short period, the logic acts normally, will it returns to high-Z output if the pixel was not hit for a long time? This requires further simulation, and the feasibility of the solution 4.1 was related to this problem.
4.3 there seems to be another priority logic inside the AERD logic. It might be duplicated with the one inside pixel digital logic. We should see if they can be merged.
5. Zhang Ying reported some current status of the analog design. The problem now is that, previously we were focusing on fast readout, thus the transistors were shrunk. However she found the mismatch of the pixel cell was increased due to the smaller transistor size, and this may leads to larger fixed pattern noise. We should further investigate this problem.