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1. Tianya reported the status of the pixel digital design. Effective effort was done to shrink the layout size of the pixel digital logic, that around 44 transistors and 30% area was saved. Some issues are still needs further verification:
1.1 The mask bit register. It is now based on the dynamic logic gate, which might has some problem when the bit needs long time holding. The held value might volatile because of the leakage current. Further simulation is needed with long simulation time.
1.2 The edge detection cell used for the analog input. Corner simulation needs to be done to check if the output pulse is long enough in all the cases, and won't suffer from the short delay of the buffer.
1.3 Zhang Ying proposed that the mast bit NAND gate move to the input of the latch. needs to be checked.
1.4 The short width glitches reported, will it cause any problem in all the corners?
1.5 Zhang Ying will soon give the requirement of the calibration bus and its generation towards Tianya and Zhang Liang. She suggested that the calibration injection is from pixel digital part.
2. Wei Xiaomin proposed some issues and proposals that focused on the dynamic gate logic, especially the address encoder, and the possible high-Z state as the consequence. For the two proposed solutions, we agreed that to add a simply INV-LATCH for each bit of the address bus at the EOC is maybe the most reasonable scheme. The pull-up resistor scheme may need some work and we will check it later, if necessary.
3. Wei Xiaomin proposed a simplified scheme for the digital logic, to combine the priority logic in the pixel digital and the address encoder. We need to further think about it and answer soon.
4. Wei xiaomin reported some issues from the discussion with Lu Weiguo.
4.1 One is related to the EOC priority readout. Now the design is partial priority in the 32-column group, token readout in the higher level. May check further if it is necessary to readout with full priority( a freeze latch may be needed)
4.2 the trigger buffer is now designed to have a depth of 8 triggers. Will check further if it is enough.
5. Li Xiaoting reported the current status of the PLL design. Based on the current process of 180nm, the highest freq seems to be 1GHz, as a conservative value.
6. We agreed that before our next meeting (Jan 7), we should gather and share all the schematics of the three critical parts: pixel analog, pixel digital, and periphery. The schematic doesn't have to be final one but should be mostly completed. Then full chip simulation and cross-check shall be done, and layout afterwards.