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1. Xiaomin proposed several interface related questions to discuss.
One is the delay of TDFor, if it is less than 25ns, in the current scheme, there will be no problem. Tianya will make sure of this value.
The other proposal is to add address latches at the EOC. This will prevent the High-Z state to propagate into the periphery logic. We agreed to add this latches, but the detailed schematic has to be further defined between Tianya and Xiaomin.
Xiaomin suggested that we add a small buffer for every column signal from the periphery, and every output signal into the periphery. This will make the pixel array logic to be isolated with the periphery, and there is no need to consider the driven ability between two parts. We also agreed with this proposal.
2. Zhang Ying reported some layout notice related to the Deep P-well and Deep N-well. It only affects the periphery layout. The best way for the layout is to make all the PMOS located in DPwell, and the NMOS located in DNwell. This will make a best isolation, however maybe too complicated in reality. We will follow the standard way, that to do the layout in a normal way first, and then to put every independent block located within DNWell. Finally, to surround the DNWell with a ring of DPWell. This makes the layout easier, with necessary isolation.
3. Tianya confirm that IFAE will do the parallel design based on the discussed scheme 1 & 2c.
4. Every part should begin the layout asap. Weiguo & Wei will do the cross check and chip simulation in parallel.
5. The next meeting will be after the Spring Festival.