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1. Wei Wei reported some detected bugs/issues/phenomena in the chip simulation, and will further make sure with the designers. It included analog simulation accuracy, array bus delay evaluation, discussion of the address encoder, impact on the read control of periphery, and some detected problems based on the preliminary simulation on the real pixel digital circuit.
Now most of the simulation focused on a single column. The next step will be further verification on a small array.
2. Tianya reported some modified design on the ALPIDE AERD logic. The proposed modification will speed up the address validation by half a cycle. We agreed to use the modified architecture for the sch1 address encoder, but thorough simulation should be done on this architecture, for it has not been verified in MOST1.
3. Wei Xiaomin reported their current work on periphery logic design. DFT was added to do the self test for the periphery logic and memory. One thing to make sure is: if the two schemes, 1 & 2c, can be unified into one timing, especially to be readout at the same clock edge. Wei Wei and Tianya will make sure on the pixel level, and Xiaomin will try to do the parallel design in the periphery.
4. For the periphery layout, Xiaomin needed the pin sequence in the pixel level, and Zhang Ying and Tianya will help to make sure of that.
5. It is announced that this version of design should be tapeout in May. The estimated value are: pixel array of 64row*196(or 200)col, about 2/3 area will be prepared for the pixel array+periphery+bias+PLL, and the rest will be served for the other blocks. The pads of the chip should be only placed at the bottom edge.