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1. Tianya reported the pixel digital status. Two schematics based on ALPIDE and FE-I3 were almost ready. Both schemes include slow control and pixel logic.
One issue discussed was the "strobe" signal that was needed for ALPIDE scheme. It seems to be replaceable with an edge detection blocks, with increasing cost of the area. However, it seems to be difficult in reality to be provided in triggerless mode, and will increase some dead time. Tianya will further evaluate the possibility to eliminate this strobe signal.
The other point is that the edge detection will fail at the worst case when it was used together with DFF. Now the DFF has to be changed into D-Latch from the standard cell lib. Tianya will further check this issue and to see if the D-latch can be simplified.
2. Wei Wei reported a simulation result when considering a strong wire buffer. The results showed that both the fastor to read delay and FDA were smaller than 25ns at the worst case. Wei will further check this with separated periphery logic.
3. Wei Xiaomin reported some consideration of chip configuration and multiple chip selection. We agreed that we will use the scheme that: the Chip selection will be loaded by a serial chain through multiple chips, while the SPI configuration chain will be gated by the chip selection flag.
She also reported some pin arrangement consideration and requirement when preparing for the periphery layout. Tianya and Zhang Ying will soon provide the general sequence based on MIC4 design.