MOST2 chip design meeting

Monday 1 Apr 2019, 08:00 → 18:00 Asia/Shanghai

1. Li Long reported some TCAD simulation results of the sensor. 

     CCE simulation was focused and there were some discussion on the definition of CCE. Finally the report should give the result while CCE was clearly and reasonably defined.

     The simulation of the charge collection time was compared with the tested results of JadePix1. However, the tested result was not confirmed. 

     Another question was the NIEL simulation, while there was a unreasonable rise of the CCE after radiation. The definition of the CCE should again be made clear.

  2. Xiaoting reported the design status of the PLL block and the serializer.

     Because of the large technology node, the highest frequency of the PLL at the worst case is only 2.48GHz. Therefore we agreed that the better way was to set the PLL central frequency to be at 1.28GHz.

     The configuration bits of the PLL will be provided from SPI.

     The sampling clock of the serializer will be provided from the periphery. While in trigger mode, the sampling clock will be 5MHz, and in triggerless mode 160MHz. The data clock of the serializer will be provided from PLL itself. The reference clock of the PLL will be provided from FPGA directly. The reference clock will be single-ended, and the probe signal as well. 

08:00 → 08:20 TCAD simulation

Slides LongLI_20190401_TCAD_simulation_work_on_TJ.pptx

08:20 → 08:40 PLL design

Slides Lixt_MOST2_PLL_Weekly_Report_20190401.pptx