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1. Xiaomin reported the recent progress of the periphery layout:
i. the first trial of the full layout (in 512*1024 scale) was done. The synthesis process is relatively slow, therefore it requires about two weeks for the final layout.
ii. For the current scale of a 192col*64row array, it should be faster.
iii. We agreed that the Metal-6 layout should be reserved in the periphery layout, to let the external power supplies go into the pixel array.
iv. The first version of pixel layout and DAC, with the interface position defined, should be provided to periphery no later than April 20.
v. The preliminary floorplan of the chip was also discussed. Please refer in the slides that are going to be given in the CEPC workshop in London.
2. Tianya has almost finished the pixel layout for FE-I3-like approach. The decoder was left unfinished. Wei Wei will help to do the layout of this part. Tianya will do the layout for ALPIDE-like approach.
We agreed the layout constraint in the pixel layout that: it is better that M1~M3 be used for local interconnection, M4 for global signal connection, and M5,M6 for the global power supply.
3. Xiaoting reported the status of PLL design. New pin definitions were discussed with periphery.
4. The scheme of I/O organization should be defined asap. Three possible ways: 1. standard IO based, with a self designed IO set for -6V substrate. 2. CCNU IO based, all self designed, with possible risks of ESD. CCNU has agreed to share the lib; 3. CERN IO based, all self designed, but proved. This may has some potential politic problem.