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1. Tianya reported the progress of the digital cell layout. There was a modification of the schematic for the ALPIDE scheme, that the input latch for the hit register was replaced by a DFF, the for the reset, a delay cell should be used. The reason was the strobe signal needed for the ALPIDE can not be provided. However due to the lack of crosscheck simulation of this modification, Tianya should guarantee the correctness of this modification. The layout of the column of ALPIDE will be ready before the end of this week.
2. Wei Xiaomin proposed some modification for the periphery.
One proposal is to make the SPI interface of several chips in serial, so as to decrease the Chip-Selection indicators and wire number. However, the chips are simply connected, without any redundancy or protocol. It cannot avoid the problem that if one chip die, the rest chips on the follow chain will fail, and thus lower down the system reliability. Therefore this proposal is not preferred.
The other proposal is to make the load_c & load_m for the SPI configuration to be generated by software and automatically. However, in order to guarantee the testability, and avoid any possible bugs in the coding, it is necessary also keep the direct connection of load_c & load_m from the IO pad.
She also asked to provide the layout of the global analog power supplies, however it is not possible currently, because it requires all the layout of other blocks ready. We agreed that the periphery makes the first layout with TopMetal fully covered, and then further modified according to the full layout.
3. The weekly plan of this week was discussed. We should finish the pixel array by this week, and verify all the schematic. Other blocks should also finish their first version so that the chip floorplan and the pin arrangement can be defined.
4. Jia Wang reported that the LDO design may not catch up of this MPW. However, this means in the final version, there will be no LDO, because every blocks was supposed to be verified in this MPW, and only to be integrated in the 2nd MPW after verification. Still, the LDO should be designed according to the final requirement if the block find chance to be tested in this tapeout and for the final version.
5. For the chip design review next week, some report should be prepared for the related blocks, especially for the analog, digital, & periphery.