MOST2 chip design meeting

Monday 16 Sep 2019, 08:00 → 18:00 Asia/Shanghai

 1. Wei Wei reported the simulation results based on the pull-up transistor design with control logic. The gates of the transistor were connected to the FASTOR/VALID. Both the timing and functionality will not be affected while the high-z state is eliminated. It is preferred than the uncontrolled pull-up scheme, because it needs no more modification on other logics.

  2. Tianya did parallel simulation also on the pull-up scheme. It seems the tri-state buffer can be simplified as a standard buffer, because the high-z state is no more existed.

  3. The next step is to verify the pull-up scheme in the full matrix. First is to verify if "READ" has to be modified into 37.5ns, or can still be 25ns; Then the scheme has to be verified with real circuit and all the RC parameters. It should also be evaluated if modified-ALPIDE can be simplified so as to ease the layout design.

  4. The test board production was finished, waiting for the component order. The test code will be programmed by IHEP & IFAE in parallel. 

08:00 → 08:20 high-z elimination

Slides Weiw_20190916.ppt

08:20 → 09:20 verification of pull-up cell

slides VERIFICATION_OF_PULL_UP_CELL.pdf