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1. Test PCBs are ready, while components still need 2~3 weeks for order. The chip is expected to be delivered on Oct. 10
2. Tianya reported a new proposal with super-pixel design to improve the capability to distinguish close hits. The scheme was based on FE-I3, while the former scheme record the time stamp at the EOC, the new scheme proposed to record time stamp in a 2*2 pixel region. In this way, the time stamps of two close hits will not be the same.
By discussion, we thought generally the new scheme work as it proposed. However, before it took too much effort, we suggested that it is better to evaluate both the extra power and area cost. For power, the new scheme has to fannout a 40MHz 8bit time stamp into the pixel array with a heavy bus load, while the old scheme only need to fannout a fastor every 8.3us by average. For the area, on one hand, a 8-b RAM has to be place in the super-pixel, and on the other hand, a 8b input and 8b output time stamp bus has also be added based on the current layout, which seems to be very difficult.
3. Xiaomin reported a proposal for the periphery logic improvement in this version. The major goal is to shrink the area occupation. The idea is to use SRAM to replace the DFF, whose bit size is smaller. The other possible solution is to integrate compression logic that can further save the register depth.
4. Wei Wei reported some simulation result, that further prove the pull-up scheme and address latch scheme can work with full array RC parasitics for the FE-I3 scheme.