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1. Tianya gave some evaluation reports on the scheme. For the proposed scheme about super-pixel, when clock buffers were added, the average power will increase by 132mW/cm2, which was not acceptable. However, we suggest that maybe the super-pixel scheme can still be evaluated, which is based on the current FE-I3 architecture, not to modify the time stamp, but only to make several pixel share the FE-I3 logic. The area cost should be saved. However it will add further error on time stamp, so it is needed to be evaluated if the extra time error is acceptable from the physics point of view.
He also simulated our former schemes and updated schemes with pull-up. It showed that the power consumption was well controlled than the former ones during the initial stage. Also the average power was less than 10mW/cm2， which was also small. There was one suspicious problem that maybe due to the pull-up transistor, that during the column hit, the peak current was high. We need to further check this issue.
2. The chip fabrication is progressing to 97%. It is expected to be received very soon.