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1. Tianya reported some evaluation results about the proposed super-pixel scheme. For layout, it was found that to put a full set of 8-bit time stamp bus was not possible, maybe only 4-bit bus is allowed. For the power estimation, we have some doubts on the simulation results. We suggested that the simulation should consider the real working frequency, that the latches act when every 8.3us a column will be hit, and the time stamp bus should also include the full parasitic and buffers.
We suggested Tianya to evaluation the feasibility of the proposed scheme, and to evaluate how much we can gain and how much we should pay for that(area, power...)
2. Some timing definition was discussed with Xiaomin. We will generally still keep two parallel scheme of FE-I3-like and ALPIDE-like scheme in this tapeout, and to occupy a full area of 5mm x 5mm.
3. Jianing reported that the component ordering is also finished, and we are going to make some component soldering for 15 PCBs in advance.
The test firmware was in progress, and can have a general framework on Oct. 22. Some further debugging may needed when work with the real chips.
No further news for the chip, and they should be received more or less this week according to the original schedule.