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1. Tianya reported some simulation results with RC modeling. The results generally agreed with the post simulation, and showed TCPX2 made some improvement on timing. However, there was still some simulation that could not be explained, and needs further verification. The periphery circuit is under tested in IFAE, and generally showed the same behavior as what was tested in IHEP.
2. We discussed the PIN list of the TCPX2 chip, and are going to design the test board for the chip. The chip will be treated as a normal die for a normal test board firstly. The inter-chip connection will be evaluated after all the test are done, with another new designed board.
3. Zhang Ying reported some further test results on the pixel analog circuit. The time walk responses were thoroughly tested and swept with different bias condition. The behavior was similar as in the simulation, however the tested time walk seemed one time larger than the simulation. The best time walk tested was 76ns, while in simulation it was 33ns @ 300e-. It may because of the imperfect biasing.
Some suspicious phenomena were also discussed, yet we can not well explain them, and need further check.
It was also noticed that when using the internal biasing circuit, multiple analog output pulses can be found in some range of the VRESET. However, when using external biasing, the analog output was normal. needs further check.
It was found that the PWELL network might be vulnerable to the ESD, and one must be careful when tuning the PWELL voltage from 0V to minus. It is suggested all the test be initiated from 0V for the PWELL.
4. The test setup was delivered to NWPU and was found that it can run functionally. Further test will be done.