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Nov 26 – 27, 2021
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宁 韩 (西安交通大学)



The output pulse current signal of Si detector has a wide response dynamic range, and its dynamic range is fC~pC, which may span 3~5 orders of magnitude. Therefore, it is necessary to carry out wide dynamic and high integration front-end readout circuit research. In this paper, a 0.18μm process is used, and a single channel chip area is 0.23mm×0.15mm. A three-stage gain adjustment circuit is designed to meet the wide dynamic range of the detector output signal. In order to provide a stable DC current bias for the circuit, a reference current source circuit is designed. The simulation results show that the performance of the readout circuit basically meets expectations. Based on the simulation results, the main factors affecting the signal-to-noise ratio of the circuit are analyzed, and the main technical ways to reduce the front-end ASIC noise are discussed.

Primary author

宁 韩 (西安交通大学)


Yanli Xiong (Xi an Jiaotong University) Dr 书焕 刘 (西安交通大学) Mr 勇 马 (西安交通大学) Mr 双瑛 刘 (西安交通大学) Ms 君 张 (西安交通大学)

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