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Nov 26 – 27, 2021
Asia/Shanghai timezone

基于延迟锁相环结构的TDC原型ASIC设计

Nov 27, 2021, 10:28 AM
18m

Speaker

东磊 郭 (中国科学技术大学)

Summary

本实验室在180nm CMOS工艺下研发了一款基于延迟锁相环结构的16通道TDC,测试结果显示在156ps bin size基础上的时间精度好于60ps,动态范围为20us,DNL和INL分别好于0.13LSB和0.15LSB。

Our lab developed a 16-channel TDC based on delay-locked loop structure under 180nm CMOS process. The test results show that the time precision is better than 60ps with 156ps bin size, the dynamic range is 20us, DNL and INL are better than 0.13LSB and 0.15LSB respectively.

Primary author

东磊 郭 (中国科学技术大学)

Co-authors

家军 秦 (USTC) 松富 蓝 (University of Science and Technology of China) Dr 雷 赵 (中国科学技术大学)

Presentation materials