1. If you are a new user, please register to get an Indico account through https://login.ihep.ac.cn/registIndico.jsp. Any questions, please email us at helpdesk@ihep.ac.cn or call 88236855.
2. The name of any uploaded file should be in English or plus numbers, not containing any Chinese or special characters.
3. If you need to create a conference in the "Conferences, Workshops and Events" zone, please email us at helpdesk@ihep.ac.cn.
21-26 May 2017
Beijing International Convention Center
Asia/Shanghai timezone
Home > Timetable > Contribution details

Contribution Poster

Trigger and data acquisition systems

A Prototype of an ATCA-based System for Readout Electronics in Particle and Nuclear Physics


  • Ms. Min LI

Primary authors


The new-generation particle and nuclear physics experiments are run with more channels and larger amount of data transmission. For example, in the high speed and high resolution waveform digitization, more than 10 Gbps date rate in one channel is necessary, thus the traditional architecture based on shared-bus, such as PCI and VME, is of low efficiency and inevitable deadtime. A prototype system based on the Advanced Telecom Computing Architecture (ATCA) is designed, with the purpose of achieving high bandwidth data transmission and less deadtime for the readout electronics in particle and nuclear physics experiment, especially for the waveform digitization.
The prototype system is designed based on the PICMG 3.0 ATCA standard, including hub board and several node boards, all on an 8U shelf. Two methods of point-to-point links, Peripheral Component Interconnect Express TM (PCIe) and fiber, are researched to evaluate the connection of the hub board and node boards through the ATCA dual-dual star backplane. Each node board is designed to produce above 20 Gbps data by Gsps Analog to Digital Converter (ADC) or Filed Programming Gate Array (FPGA), which is also for controlling, data buffering and transmission. The hub board collects all the data transferred from node boards via ATCA backplane. With the abundant inner connections and logic resources in FPGA on it, event selection, data packing and real-time correction can be implemented. Meanwhile, a Gigabit Ethernet port connected to the PC is designed for processed data output.
The initial board testing has been performed and the prototype system has proven to be successful. More laboratory tests will be conducted for further study.