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21-26 May 2017
Beijing International Convention Center
Asia/Shanghai timezone
Home > Timetable > Contribution details

Contribution Poster

Semiconductor detectors

Development of highly compact digital pixels for the vertex detector of the future e+e- collider

Speakers

  • ZHOU YANG

Primary authors

Co-authors

Content

For the advantages of reduced power dissipation, higher readout speed, and less insensitive sensor area, pixel-level discrimination becomes the necessary solution of the pixel sensors for the vertex detector in the future e+e- collider. However, the complexity of digital pixels always leads to an increased pixel dimension which is contrary for vertex detector to obtain a high spatial resolution.
In order to push the dimension limit of digital pixels while maintaining other key parameters such as power consumption and readout speed, a CMOS pixel sensor (CPS) prototype including two versions of highly compact digital pixel (pitch size = 22μm) has been designed in a 0.18 μm CMOS Image Sensor Process. It contains 112 x 96 pixels, with a size of 2.9 x 3.3mm2. The sensing diode in each pixel is AC-coupled with following electronics and biased with positive high voltage about 10 V, which could fully depleted the thin epitaxial layer. Comparing with traditional biased diode (≈ hundreds mV), the equivalent capacitance of the sensing diode is 30% less for the same diode dimension based on the simulation, thus the effective signal value converted by the diode is 30% higher, also the Equivalent Noise Charge (ENC) contributed by the following electronics is proportional less. Take advantages of the depleted CPS, two simple in-pixel digitization structures are proposed. The two structures are trade-offs between high precision and simplicity which guarantee a compact pixel dimension with certain signal over noise ratio. Both of them composed with an amplifying stage and a precise comparator. The main difference of the two versions is the amplifying stage is a differential amplifier or two stage single-end amplifiers. The prototype is operated in rolling-shutter mode, the processing speed is 100 ns/row and 80 ns/row respectively for the two versions. The design details for the trade-off consideration and operation principles will be presented.